In a digital camera, an object is imaged by a CMOS image sensor and a taken image is stored or displayed.
When noise is superimposed on the power supply voltage in the CMOS image sensor, a signal level readout from an output signal line is affected. Accordingly, a technique for suppressing such voltage variation is proposed (for example, JP-A-2009-225021 (Patent Document 1)).
FIG. 1 is a diagram showing a configuration of an image sensor in related art. Only one pixel is shown in a CMOS image sensor 1. Necessary power is supplied to a RST driver 11 and a TRG driver 12 from a pixel power line 25. Necessary power is supplied to a SEL driver 13 from a SEL driver power line 26 connected to the pixel power line 25 through a switch 20.
In order to prevent variation, a voltage of a capacitor 16 to which a voltage of a photodiode 15 is transferred is read out just after reset and at a timing when a given period of time has passed after the reset, and the voltage difference will be a pixel signal outputted from the photodiode 15.
When the voltage of the capacitor 16 is reset, the RST driver 11 turns on a FET (Field Effect Transistor) 17 at a timing when a control signal RST is inputted and clamps the voltage of the capacitor 16 at a reference voltage. At this time, the SEL driver 13 drives a FET 19 through a SEL line 27 in accordance with a control signal SEL, therefore, the voltage of the capacitor 16 is amplified by a FET 18 and outputted to a signal output line 24 through the FET 19.
The photodiode 15 generates electric charges corresponding to a light receiving amount from an object incident on the photodiode 15 after that. When a control signal TRG is inputted at a given timing, the TRG driver 12 turns on the FET 14 and transfers the electric charges of the photodiode 15 to the capacitor 16. At this time, the voltage of the capacitor 16 is amplified by the FET 18 and outputted to the signal output line 24 through the FET 19.
When voltage variation occurs in the pixel power line 25 due to some reason in the case where the switch 20 is in an on state, the variation is transmitted to the SEL line 27 through the SEL driver 13 and further transmitted to a charge storage unit FD through a parasitic capacitance 22. Then, the variation is outputted to the signal output line 24 through the FETs 18 and 19. The variation is also transmitted also through a stray capacitance 23. The voltage variation is transmitted to the signal output line 24 in this manner.
In order to prevent the above, the switch 20 is turned off at a timing when the voltage of the capacitor 16 is read out. As a result, a potential of the SEL line 27 is in a floating state at a high level and voltage variation can be suppressed. That is, PSRR (power supply rejection ratio) can be improved.